To achieve a satisfactory degree of intensity resolution in a display system using pulse width modulation (PWM), some display time periods (bit times) need to be shorter than the time required to reload the pixels of the SLM. To accomplish these short bit times in some SLMS, for example in a digital micromirror device™ (DMD™), rows of modulator elements are portioned or grouped together so that the entire device doesn't have to be loaded at one time. However, in modern systems where the bit times are continuously becoming shorter and shorter, it is possible for the short-bit (bit 0) time to be shorter than even the partitioned block loading time plus mirror settling time.
FIG. 1a is a diagram showing a conventional approach, called reset-release timing, used in a phased system where the block loading time plus the mirror settling time is longer than the bit 0 time. In this approach, at the end of the bit 0 period the mirrors are released to a flat state and held while the next bit is loaded. This is accomplished by turning the mirror bias OFF and allowing them to float around the 0° position. FIG. 1a shows the data to be loaded into memory, the reset timing, and the reflected light response from the mirrors. While the mirrors are in their selected state from normal bit A 100, the reset-release (rr) bit is loaded 101 into memory, but the mirrors are not reset immediately. At the appropriate time (after delay), a reset pulse 102 occurs setting the mirrors 103 according to the rr data in memory. Then at the end of the short bit 0 period, the mirrors are released 104 by turning OFF the mirror bias 105. In the absence of a bias, the mirrors go to a flat state 106 and remain there while data for the next normal bit B 107 is loaded into memory. The bias is then turned back ON 108 and the mirrors assume their bit B positions 109. This approach allows some stray light to get into the lens aperture and cause undesirable artifacts.
FIG. 1b illustrates the timing for the reset-release method of FIG. 1a. This diagram shows a normal bit A being loaded 10 and reset 11, then the reset-release (rr) bit is loaded 12 but not immediately reset in the normal fashion. Then at the appropriate time the rr bit is reset 13, allowing the mirrors to go to their appropriate state, and released 14 at the end of the bit 0 time period, when the mirror bias is turned OFF. Once released, the mirrors go to and remain in a flat (approximately 0°) position while the next bit B is loaded 15. Once loaded, the mirror bias is turned back ON 16 allowing the mirrors to go to their new state (Bit B) at which point the normal sequence of loading 17 and resetting 18 the next bit continues. The problem with the reset-release method is that the flat mirrors lead to additional optical artifacts, such as stray light entering the aperture causing horizontal lines at the reset block boundaries, a “venetian blind” effect across the reset blocks, and lower system contrast due to higher dark levels.
The clocking method of the referenced patent application, Ser. No. 60/221,733, called jog-clear, addressed the needs and shortcomings listing above by turning the mirrors OFF, rather than allowing them to float, while loading the next bit after the short-bit. Solving this short-bit generation time problem is not a trivial matter and in this approach is complicated by the fact that the combination of data and reset operations need to be performed independently on each block in a phased manner. In addition, matters are further complicated by the additional restrictions that a block clear cannot be performed on one block while loading another block. However, the jog-clear method addressed these needs and provided a higher performance solution, albeit with some limitations as to device type and bit ordering. Major advantages of the jog-clear method as described in the referenced application include: (1) elimination of visible lines at block boundaries, (2) elimination of the so-called “venetian blind” effect, and (3) significantly reduced black level.
In the jog-clear method, a block clear is performed during the short bit period (s—time). As a result, instead of a reset-release of the mirrors (with unstable flat mirrors), a clear-reset latches the mirror into the OFF (dark) state for the duration of time it takes to load the memory for the next normal bit. The method centers around the technique used to achieve this dark state for very short periods of time. An aspect of the method is the requirement that the SLM and controller be capable of being cleared with a field of binary zero data generated internal to the device and with multiple row per clear cycle, while not affecting the data in any other reset block.
FIG. 2a is a diagram showing the jog-clear method of the referenced invention for a phased system. Although this looks similar to the reset-release method of FIG. 1a, the difference is that the jog-clear bit is loaded and then the mirrors are cleared to the dark state in phased blocks. FIG. 2a shows the data to be loaded into memory, the reset timing, and the reflected light response from the mirrors. While the mirrors are in their selected state from normal bit A 200, the jog-clear bit is loaded 201 into memory, but the mirrors are not immediately reset. The mirrors are then reset at the appropriate time 202 (after delay) to display 203 the short bit. Then the memory is loaded with clear data (all binary 0's) 204 and a reset pulse 205 clears all the mirrors in a block precisely at the end of the short bit period, forcing all mirrors to the OFF (dark) state 206 while data for the next normal bit B is loaded 208 into memory. Finally, a reset pulse 209 causes the mirrors to go to their normal bit B state 210. Notice in this diagram that during the dark state, while load B 208 is underway, the bias voltage 207 is still applied to the mirrors and since all memory locations are set to binary 0, all mirrors are OFF.
FIG. 2b illustrates the timing for the jog-clear method of FIG. 2a. This diagram shows a normal bit A being loaded 20 and reset 21, then the data for the short bit is loaded 22 but not immediately reset in the normal fashion. Then at the appropriate time this jog-clear bit is reset 23 setting the mirrors to their short bit state. Next, the clearing function is applied to terminate the short bit at the appropriate time. The clear data is loaded 24 and the mirrors reset 25 at the end of the short period, but the mirror bias is still applied so that the mirrors are turned OFF (dark) while bit B is loaded 26 and reset 27. The normal load bit 28 and reset mirrors 29 sequences then continues through the next frame.
The seemingly straightforward process of placing the block clear between two block loads is further complicated by the fact that in micromirror devices used with jog-clear, a clear on one block of data cannot occur while another block is being loaded. Notice in the example shown in the diagram of FIG. 2b that when jog-clear in block 6 220 occurs, there is no other activity going on in the device. This mandates a spreading out in time of the DMD block loads, which causes a skew 221 (change in slope) for the short-bit block sequence relative to the slope 222 for a normal-bit block sequence. This change in slope produces times for bit A (from reset 21 to reset 23) that are shorter for first reset blocks (e.g., 0, 1, 2, . . . ) than for later reset blocks (e.g., . . . , 5, 6, 7). Similarly, the times for bit B (from reset 27 to reset 29) are longer for the first reset blocks than for blocks reset later in the cycle. If not corrected, this condition would cause non-uniform weights for bits A and B and thus visible artifacts. This skew is acceptable as long as it is removed elsewhere in the sequence, as it is by the jog-clear method. To remove this skew, the bit-ordering restrictions described below must be applied.
But, the jog-clear method adds bit-ordering restrictions to the system sequence. For example, in a 9-bit system where bits 8 and 9 are normal bits, and bits 0 and 1 are jog-clear bits, one of the following bit sequences must be used:                (1) sandwich skew: 9-0-9; a jog-clear must be surrounded on both sides by the same bit, or        (2) opposite adjacent skew: 9-0-8 . . . 8-9; the bits surrounding the jog clear bit must be adjacent in the opposite order elsewhere in the sequence(s) and must be reset with the same skew as that of the jog-clear bit, or        (3) paired skew: 9-0-8 . . . 8-1-9; the jog-clear bit may be paired with another jog-clear bit, surrounded by the same bits in opposite order.As FIG. 2b shows, inserting block clears between block loads also requires the external manipulation of the DMD row address. For instance, after the load of bit B 26 for block 0, the DMD address must be moved down to block 2 to continue the clear 24 for block 2. After that block clear, the address must be returned to the top of block 1 to continue the load of bit B for block 1. This process, where the DMD address jogs back and forth as the block clears occur, requires both an external control circuit to manage it and a DMD that can respond appropriately. Some DMDs have random row address capability for which the control circuit simply computes the next row address and supplies it to start each block operation. Another class of DMDs can only adjust the row address sequentially forward or backward. The control circuit for these DMDs sets a count direction and directs the DMD to count the number of times necessary to advance the row count to the correct block. Some of these DMDs can advance row addresses in multiple rows per count. The control circuit can use this fast counting mode to decrease the counting time and minimize the skew.        
In summary, with the jog-clear method the reset-release and bias-on operations are replaced with simple reset operations to virtually eliminate the artifacts associated with reset-release. However, in this method there can be no conflict between block clears and block loads. In other words, with jog-clear, when one block is loading, no other block can be clearing. Because of this requirement there is an undesirable time skew introduced in the timing, causing significant limitations on bit ordering.
What is needed is a new method that overcomes the problems of reset-release without introducing the jog-clear bit-ordering restrictions. The method of the present invention, called fast-clear, uses embedded-block clear hardware to accomplish this need.